Parallel-to-serial converters are used across various computing devices and for various applications. For instance in DDR-DRAM semiconductor memories, a double data rate input to semiconductor memory is converted internally into a single data rate and written in parallel to the semiconductor memory. For a read access, the stored data in the semiconductor memory that is stored in parallel is converted into a serial data stream for output. An interface circuit of the semiconductor memory is equipped with a parallel-to-serial converter for such conversions.
In the simplest case, a parallel-serial converter is designed as a controllable shift register. The parallel-to-serial converter has a number of cascade-connected flip-flops corresponding to the number of input terminals. Furthermore, a control signal generated by means of a multiplexer may be provided for controlling the shift register. The construction and the method of operation of such a parallel-to-serial converter designed as a controllable shift register are known in many instances.
For a typical parallel-to-serial converter, the single multiplexer is used for parallel loading of an entire N-bit word into a shift register. The shift register then shifts the loaded data to generate serial data. After the N-bit word is shifted out, another N-bit word is retrieved for parallel loading into the shift register. The latency of such parallel-to-serial converter is very low due to its simplicity. However, the amount of power used to operate such parallel-to-serial converter is quite high. Therefore, there remains a desire for providing a parallel-to-serial converter that has low latency and low power consumption.